A non-volatile flash memory device is known to store charges in a floating gate by means of either Fowler-Nordheim tunneling or hot-electron injection through a thin tunneling-oxide layer from a semiconductor substrate for programming operation and to remove or erase charges stored in a floating gate by means of Fowler-Nordheim tunneling through a thin tunneling-oxide layer to a semiconductor substrate or to a control gate for erasing operation. Based on the specific cell structure chosen, flash memory cells may be made up of a stack-gate structure.
A typical stack-gate structure of prior art flash memory cells is shown in FIG. 1A and FIG. 1B. More particularly, FIG. 1A shows a schematic view of high density floating gate flash memory elements forming a NAND-type flash memory array having floating gates self-aligned with shallow trench isolation (see M. Ichige et al., “A novel self-aligned shallow trench isolation cell for 90 nm 4 GBit NAND Flash EEPROMs”, 2003 Symposium on VLSI Technology Digest of Technical Papers).
Referring now to FIG. 1A, a plurality of shallow isolating trenches 2 are provided on an integrated circuit substrate 3 to define a plurality of active regions 1. A control gate 4 crosses over the shallow isolation trenches 2 pattern. A floating gate 5 pattern is disposed between the control gate electrode 4 and the active regions 1. As illustrated in FIG. 1A, the flash memory element further includes a tunneling-oxide layer 6 pattern being arranged in between the floating gates 5 and the active regions 1 and an inter-gates dielectric layer 7 being arranged in between the floating gate 5 and the control gate 4. The inter-gates coupling dielectric layer 7 is typically of an oxide-nitride-oxide (ONO) structure and includes first 8, second 9 and third 10 layers of silicon oxide, silicon nitride and silicon oxide, respectively. The flash memory element further includes a metal layer 11 deposited on the control gate 4 and a hardmask layer 12 arranged on the metal layer 11
Referring to FIG. 1B, typical high density floating gate flash memory cells realized in NOR-type structure as sectioned through its source/drain-regions 13 and channel regions 17 are shown. Similar to the arrangement of FIG. 1A, floating gates 5 are placed above silicon substrate 3 having a tunneling oxide layer 6 arranged in between. Control gates 4 and floating gates 5 are separated by inter-gates dielectric layer 7. Bit-line 14 has a plurality of bit-line contacts 15 to contact drains of active regions 13 of the memory cells.
Referring now to FIGS. 5A and 5B, schematic views of a typical NAND-type flash memory array and a typical NOR-type flash memory array, respectively, are shown. FIG. 5A is a top plan view of a NAND-type array having a plurality of memory elements arranged in rows and columns. FIG. 5A shows several NAND-strings, each of which comprises a plurality of flash memory elements. Each NAND-string is respectively connected to one bit line BLk defining a column, and, in each NAND-string between a bit line contact 16 and a common ground line CG, a plurality of flash memory cells and two select transistors are connected in series. A plurality of word lines WLk and two selection transistor lines SG1, SG2 defining rows are crossing the bit lines, each of which word lines are connected to control gate terminals of the memory elements of a row, while selection transistor lines are connected to the gates of corresponding selection transistors. Between adjacent bit lines, bit line pitch F may be identified.
FIG. 4B is a top plan view of a NOR-type array having a plurality of memory elements arranged in rows and columns. Contrary to the NAND-type array of FIG. 4A, each bit line BLk is connected to each flash memory cell of a column, and, as with the FIG. 4A NAND-type array, each word line WLk is connected to each control gate terminal of a row. Between adjacent bit lines, bit line pitch F may be identified.
Recently, and especially in view of modern portable equipment as MP3-players and digital still cameras, the demand of low-cost and high-density mass storage flash memories has increased dramatically. Therefore, one of the most important issues for low-cost and high-density mass storage flash memories is a reduction of the memory cell size. However, in down-scaling flash memories a lot of problems arise, such as pattern nonuniformity and narrow process margins. Also, parasitic coupling noise increases, which may especially cause severe problems relating to adjacent floating gates in NAND-type memory cell arrays. Moreover, since tunneling-oxide layer may not be scaled down markedly in view of the fact that such scaling down is detrimental to programming and retention characteristic of the memory cell, reducing of channel lengths may also lead to an increase in the so-called short channel effects, which, however, should be avoided in any case. Otherwise, especially in NAND-type memory cell arrays having a plurality of memory cells connected in a serial array, reducing of channel width may lead to a decrease of the sense current through the memory cells, for which reason, signal-to-noise-ratio is deteriorated. The latter phenomenon is the reason why multi-level NAND-type memory cell arrays actually are realized to have 16 memory cells per string in a maximum.
It is well-known to improve scaling down characteristic, and more particularly, to increase sense current through miniaturised memory cells, in realizing the memory cells as so-called FinFET-memory cells (see for example U.S. patent application 2003/0042531 to Lee et al.). In such FinFET memory cell a first oxide film is formed on a surface of a silicon substrate and a fin active area is vertically formed on the first oxide film with a narrow width. On top and at both sides of the fin active area a gate tunneling oxide film is formed. Further a floating electrode is formed on the surfaces of the gate tunneling oxide film and the first oxide film for storing electric charges. Further, an inter-gates oxide film is formed on the surface of the floating electrode and a control electrode is formed on the surface of the inter-gates oxide film. While such FinFET-memory cells may actually succeed in enhancing signal-to-noise ratio, they, however, are usually not suitable for application in a high-density mass storage array due to a too large-sized floating gate.
Other solutions especially for overcoming the above-identified problem of reducing signal-to-noise ratio (see for example U.S. patent application 2003/0178670 to Fried et al.) comprise floating gates to be splitted in two parts by specific manufacturing methods, which, however, because of unavoidably occurring process variations may lead to a unsymmetric programming effect and erasing effect, respectively.
Furthermore, convenient manufacturing methods as disclosed in the above-cited documents may not lead to a high-dense architecture of mass storage flash memory devices.